As the rapid development of the semiconductor process, more and more electronic products can be provided with higher performance, higher portability and more compactness. Under such a development trend, the size of the chip used for the electronic products could be remarkably miniaturized, but the integrated circuits contained in the chip would become more and more complicated. Although the photolithography technique applied on the semiconductor wafer are moving into tens nanometer scale to meet the requirements for the miniaturization of semiconductor chip, it is clear that the tens nanometer scale for the photolithography process is almost the extremity of optical discrimination. Further, the scaling down of the chip size and the design complexity of the integrated circuits also entail a multiplicity of problems, such as the crosstalk effect and the thermal issues on the chip.
In order to overcome the above-mentioned issues, a promising wafer-to-wafer stacking structure, which is also called as the three dimensional wafer structure, is provided. Please refer to FIG. 1(A), which schematically shows a conventional three dimensional wafer stacking structure according to the prior art. As shown in FIG. 1(A), a wafer stacking 100 includes a first wafer 10, a second wafer 20 and a third wafer 30, each of which consists of a substrate 12, 22, 32 and a device layer. Between the adjacent wafers, a bonding layer 13 is disposed there between for constructing the wafer stacking structure. As specifically illustrated in the FIG. 1(A), the respective device layers of the first and the second wafers 10, 20 are arranged to configure them as a face to face wafer stacking structure, while the respective device layers of the second and the third wafers 20, 30 are arranged to configure them as a back to front wafer stack. Furthermore, each wafers 10, 20, 30 further has plural circuit devices 16, 26, 36 in their respective device layer, which are electrically interconnected through the signal vias 15.
Please also refer to FIG. 1(B), which schematically shows a further three dimensional wafer stacking structure disclosed in U.S. Pat. No. 7,262,495. As shown in FIG. 1(B), the three dimensional wafer stacking 80 includes a plurality of interconnect plugs 8 for electrically interconnecting the two device layers 6, 24 of the two stacked wafers. Similar to the signal vias 15 of FIG. 1(A), the interconnect plugs 8 of FIG. 1(B) are also designed for the purpose of signal transmission between two stacked wafers.
Although it is clear that the vias 15 of the wafer stacking 100 in FIG. 1(A) or the interconnect plugs 8 of the wafer stacking 80 in FIG. 1(B) are disposed between two stacked wafers for electrically interconnecting the circuits formed in different wafers, it should be noted that these vias 15 or interconnect plugs 8 are not always extended between two solid surfaces in the device layer, such that they cannot provide sufficient rigidness for supporting the device layer. Accordingly, the low-k materials, which exist in the respective device layers and are used for allowing the conducting wires thereof being arranged closely, might be destroyed by compression stresses resulting from the stacking structure or by the thermal stresses resulting from the heat generated by the circuit devices.
In order to overcome such issues, the applicant of the present invention proposed a novel wafer-to-wafer stacking structure with at least one supporting pedestal formed between two solid surfaces in the device layer for enhancing the rigidness of the low-k material in the device layer. The relevant technical schemes are also proposed in the TW Patent Application No. 94137522 and its corresponding U.S. patent application Ser. No. 11/471,165. Nevertheless, although the above-mentioned supporting pedestal can be used for preventing the low-k materials existing in the device layer from being damaged by the stresses, it still exists the reliability issue for the low-k materials, since those low-k materials are usually made of the porous materials which are very sensitive to the humidity. Based on the above, it is necessary to find a new technical scheme to prevent the low-k materials existing in the device layer from being affected by the humidity for improving the reliability of the low-k materials used in the wafer stacking structure.